This application is based upon and claim the benefit of priority from the prior Japanese Patent Applications No. 11-276259, filed Sep. 29, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates generally to a field-effect transistor of a MOS structure (including a MIS structure), and more particular to a field-effect transistor with an improved gate insulation film and a method of fabricating the same.
FIG. 1 is a cross-sectional view showing a device structure of a conventional MOS field-effect transistor. FIG. 1 shows an n-channel type field-effect transistor by way of example. In FIG. 1, reference numeral 1 denotes a p-type silicon substrate; 2 an isolation region; 3 a p-well region; 4 an n-channel, more specifically, a region doped with impurities for controlling a threshold voltage of the field-effect transistor; 5 a gate insulation film of SiO2, etc.; 6 a gate electrode formed of a polysilicon film, etc.; 7 a source/drain region; 8 wiring; and 9 an interlayer insulation film.
In the field-effect transistor with the above structure, the gate insulation film 5 is formed of uniform material over an entire region covered with the gate electrode 6. From the standpoint of enhancement of a current drive power of the device, it is preferable to set a dielectric constant of the gate insulation film 5 at a high value. This, however, increases a capacitance of a overlap portion where the gate electrode 6 overlaps the sour/drain region 7. The increase in capacitance of the overlap portion means an increase in parasitic capacitance of the device, and it increases a delay time of the device. That is, the operation speed of the device decreases. This problem is serious, in particular, in the case of a CMOS inverter in which a mirror capacitance is present at a portion of a pMOS which is opposite to a power supply and at a portion of an nMOS which is opposite to a ground.
The capacitance of the overlap portion between the gate electrode 6 and the source/drain region 7 may be decreased if the gate insulation film is formed of a material with a low dielectric constant. Where the gate insulation film is formed of such a low dielectric-constant material, however, the current drive power of the device decreases and in this case, too, the operation speed of the device decreases. Moreover, that the gate insulation film is formed of a low dielectric-constant material means a decrease in controllability of the gate electrode 6, with which the gate electrode 6 controls a charge in the channel region. This poses a further problem that a short channel effect increases.
As has been described above, from the standpoint of reduction in capacitance between the gate electrode and the source/drain region, it is preferable that the dielectric constant of the gate insulation film be low. However, from the standpoint of suppression of the short channel effect and enhancement of the current drive power of the device, it is preferable that the capacitance between the gate and the channel region be large and, accordingly, that the dielectric constant of the gate insulation film be high. Under the circumstances, in the conventional device, it is not possible to sufficiently suppress the short channel effect and obtain an adequate current drive power, and at the same time to sufficiently reduce the parasitic capacitance in the device. This has prevented realization of a higher-speed operation of the device.
The object of the present invention is to provide a field-effect transistor which can have a high current drive power and a sufficient suppression function for a short channel effect, while suppressing a parasitic capacitance and achieving a high-speed operation.
In order to achieve the object, according to a first aspect of the present invention, there is provided a field-effect transistor comprising:
a semiconductor substrate;
a gate insulation film formed selectively on the semiconductor substrate;
a gate electrode formed on the gate insulation film;
source/drain regions formed in surface portions of the semiconductor substrate along mutually opposed side surfaces of the gate electrode, the source/drain regions having opposed end portions located immediately below the gate electrode, each of the opposed end portions having an overlapping region which overlaps the gate electrode; and
a channel region formed in a surface portion of the semiconductor substrate, which is sandwiched between the opposed source/drain regions, wherein that portion of the gate insulation film, which is located at the overlapping region where at least one of the source/drain regions overlaps the gate electrode, has a lower dielectric constant than that portion of the gate insulation film, which is located on the channel region.
According to a second aspect of the invention, there is provided a field-effect transistor comprising:
a semiconductor substrate;
a gate electrode formed above the semiconductor substrate;
a gate insulation film formed between the gate electrode and the semiconductor substrate, the gate insulation film retreating from at least one of mutually opposed ends of the gate electrode;
an interlayer insulation film formed on at least one of mutually opposed side surfaces of the gate electrode, that portion of the interlayer insulation film, which is located on a side where the gate insulation film retreats, being put in contact with the semiconductor substrate, and a void being created by the gate electrode, the gate insulation film and the substrate; and
source/drain regions formed in surface portions of the semiconductor substrate along the mutually opposed side surfaces of the gate electrode, the source/drain regions having opposed end portions located immediately below the gate electrode, each of the opposed end portions having an overlapping region which overlaps the gate electrode.
According to a third aspect of the invention, there is provided a method of fabricating a field-effect transistor, the method comprising the steps of:
forming a gate electrode over a semiconductor substrate, with a gate insulation film interposed therebetween;
forming source/drain regions in surface portions of the semiconductor substrate in a self-alignment manner with the gate electrode;
removing a portion of the gate insulation film from at least one side of the gate insulation film; and
forming a gate insulation region, which has a lower dielectric constant than the gate insulation film, at a region from which the portion of the gate insulation film is removed.
According to a fourth aspect of the invention, there is provided a method of fabricating a field-effect transistor, the method comprising the steps of:
forming a gate electrode over a semiconductor substrate, with a gate insulation film interposed therebetween;
forming a conductor film selectively on a side surface of the gate electrode;
forming source/drain regions in surface portions of the semiconductor substrate in a self-alignment manner with the gate electrode including the conductor film; and
a step of forming a gate insulation region, which has a lower dielectric constant than the gate insulation film, at a region between the conductor film and the substrate.
In the present invention, it is preferable that the dielectric constant of the gate insulation film on the channel region be set to be higher than that of a commonly used silicon oxide film. Examples of such a gate insulation film are a titanium oxide film, a silicon nitride film, a silicon oxynitride film, a tantalum pentoxide film, zirconium oxide film, hafnium oxide film, lanthanum oxide film, aluminum oxide film yttrium oxide film, scandium oxide film and a layered/mixed film of the foregoings. If the gate insulation film with such a high dielectric constant is used, the short channel effect can be effectively suppressed and the high current drivability can be realized. In addition, in the present invention, the dielectric constant of the gate insulation film on the source region and drain region is set to be lower than that of the gate insulation film on the channel region. Therefore, the parasitic capacitance is also reduced. As a result, the short channel effect can be effectively suppressed and the high-speed operation can be realized.
In addition, by creating a void in the gate insulation film on the source region or drain region, the capacitance between the source/drain region and the gate electrode can be further reduced. As a result, the short channel effect can be more effectively suppressed and the high-speed operation can be realized more effectively.
A description will now be given of the advantageous effect by which an increase in parasitic capacitance can be suppressed also by using the high-dielectric constant film as in the present invention.
FIG. 2 is a graph showing the dependency of the parasitic capacitance per unit width (a value obtained by subtracting the gate capacitance (created between the gate and channel) from the total load capacitance) upon the dielectric constant of the gate insulation film in the structure of the present invention and the prior-art structure. A curve marked by ∘ indicates a dielectric constant in a case where the insulation film under the gate is uniform (FIG. 3A), and a curve marked by xcex94 indicates a case where the dielectric constant of the insulation film under the gate is high only on the channel, and the dielectric constant on the source/drain is 3.9 (FIG. 3B). In either case, the abscissa indicates the dielectric constant of the gate insulation film on the channel and the ordinate indicates the parasitic capacitance per unit gate width.
In FIGS. 3A and 3B, the parameters of the devices are set as follows:
the gate length=50 nm
the length of overlapping portion between the gate and the source/drain=7 nm the thickness of the gate insulation film=1.5 nmxc3x97the dielectric constant of the high-dielectric constant film/3.9 the impurity concentration of the well=1xc3x971018 cmxe2x88x923.
FIG. 2 shows that the parasitic capacitance indicated by xcex94 is decreased about 30% to 40%, compared to that indicated by ∘. In the devices according to these examples, the gate capacitance is about 1 fF/xcexcm, and the total load capacitance in the case indicated by xcex94 is decreased about 10% to 20%, compared to the case indicated by ∘. Taking into account the fact that the delay time is proportional to the load capacitance, the delay time in the structure shown in FIG. 3B decreases by about 10% to 20%, compared to the structure shown in FIG. 3A. In other words, a higher-speed operation can be performed with the structure according to the case indicated by xcex94.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.